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Features
* Utilizes the AVR(R) RISC Architecture * AVR - High-performance and Low-power RISC Architecture
- 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 10 MIPS Throughput at 10 MHz Data and Non-volatile Program Memory - 2K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles - 128 Bytes of SRAM - 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security Peripheral Features - One 8-bit Timer/Counter with Separate Prescaler - One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and 8-, 9-, or 10-bit PWM - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator - SPI Serial Interface for In-System Programming - Full Duplex UART * Special Microcontroller Features - Low-power Idle and Power-down Modes - External and Internal Interrupt Sources * Specifications - Low-power, High-speed CMOS Process Technology - Fully Static Operation Power Consumption at 4 MHz, 3V, 25C - Active: 2.8 mA - Idle Mode: 0.8 mA - Power-down Mode: <1 A I/O and Packages - 15 Programmable I/O Lines - 20-pin PDIP and SOIC Operating Voltages - 2.7 - 6.0V (AT90S2313-4) - 4.0 - 6.0V (AT90S2313-10) Speed Grades - 0 - 4 MHz (AT90S2313-4) - 0 - 10 MHz (AT90S2313-10)
*
*
* * *
8-bit Microcontroller with 2K Bytes of In-System Programmable Flash AT90S2313
* * *
Pin Configuration
PDIP/SOIC
Rev. 0839IS-AVR-06/02
Note: This is a summary document. A complete document is available on our web site at www.atmel.com.
1
Description
The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Figure 1. The AT90S2313 Block Diagram
The AT90S2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general purpose I/O lines, 32 general purpose working registers, flexible Timer/Counters with compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal Oscillator, an SPI serial port for Flash memory downloading and two software
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selectable power-saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next external interrupt or Hardware Reset. The device is manufactured using Atmel's high-density non-volatile memory technology. The On-chip In-System Programmable Flash allows the Program memory to be reprogrammed in-system through an SPI serial interface or by a conventional non-volatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Prog rammable Fla sh on a mo nolithic chip, th e Atme l AT90S2 313 is a p ower fu l microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The AT90S2313 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators and evaluation kits.
Pin Descriptions
VCC GND Port B (PB7..PB0) Supply voltage pin. Ground pin. Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B output buffers can sink 20 mA and can drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port B also serves the functions of various special features of the AT90S2313 as listed on page 51. Port D (PD6..PD0) Port D has seven bi-directional I/O ports with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D also serves the functions of various special features of the AT90S2313 as listed on page 56. RESET Reset input. A low level on this pin for more than 50 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the inverting Oscillator amplifier.
XTAL1 XTAL2
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0839IS-AVR-06/02
Register Summary
Address
$3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) ... $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) ... $00 ($20)
Name
SREG Reserved SPL Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR Reserved TCCR0 TCNT0 Reserved Reserved TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL Reserved Reserved Reserved Reserved ICR1H ICR1L Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved PORTD DDRD PIND Reserved UDR USR UCR UBRR ACSR Reserved Reserved
Bit 7
I SP7 INT1 INTF1 TOIE1 TOV1
Bit 6
T SP6 INT0 INTF0 OCIE1A OCF1A
Bit 5
H SP5 - - -
Bit 4
S SP4 - - -
Bit 3
V SP3 - TICIE1 ICF1
Bit 2
N SP2 - - -
Bit 1
Z SP1 - TOIE0 TOV0
Bit 0
C SP0 - - -
Page
page 16 page 17 page 22 page 23 page 23 page 24
- -
- -
SE -
SM -
ISC11 -
ISC10 CS02
ISC01 CS01
ISC00 CS00
page 25 page 29 page 29
Timer/Counter0 (8 Bits)
COM1A1 ICNC1
COM1A0 ICES1
- .
- -
- CTC1
- CS12
PWM11 CS11
PWM10 CS10
page 31 page 32 page 33 page 33 page 34 page 34
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Compare Register High Byte Timer/Counter1 - Compare Register Low Byte
Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte
page 34 page 34
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
page 37
- - - - -
EEPROM Address Register EEPROM Data Register - EEMWE EEWE EERE
page 39 page 39 page 40
PORTB7 DDB7 PINB7
PORTB6 DDB6 PINB6
PORTB5 DDB5 PINB5
PORTB4 DDB4 PINB4
PORTB3 DDB3 PINB3
PORTB2 DDB2 PINB2
PORTB1 DDB1 PINB1
PORTB0 DDB0 PINB0
page 50 page 50 page 50
- - -
PORTD6 DDD6 PIND6
PORTD5 DDD5 PIND5
PORTD4 DDD4 PIND4
PORTD3 DDD3 PIND3
PORTD2 DDD2 PIND2
PORTD1 DDD1 PIND1
PORTD0 DDD0 PIND0
page 56 page 56 page 56 page 45
UART I/O Data Register RXC RXCIE ACD TXC TXCIE - UDRE UDRIE ACO FE RXEN ACI OR TXEN ACIE - CHR9 ACIC - RXB8 ACIS1 - TXB8 ACIS0
page 45 page 46 page 48 page 48
UART Baud Rate Register
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the Status Flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a "1" back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
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Instruction Set Summary
Mnemonic
ADD ADC ADIW SUB SUBI SBIW SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER BRANCH INSTRUCTIONS RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k k Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less than Zero, Signed Branch if Half-carry Flag Set Branch if Half-carry Flag Cleared Branch if T-Flag Set Branch if T-Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (R(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC + k + 1 if (SREG(s) = 0) then PC PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 None None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None 2 2 3 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
Operands
Rd, Rr Rd, Rr Rdl, K Rd, Rr Rd, K Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd
Description
Add Two Registers Add with Carry Two Registers Add Immediate to Word Subtract Two Registers Subtract Constant from Register Subtract Immediate from Word Subtract with Carry Two Registers Subtract with Carry Constant from Reg. Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register
Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rdh:Rdl Rdh:Rdl - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None
# Clocks
1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS
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0839IS-AVR-06/02
Instruction Set Summary (Continued)
Mnemonic
MOV LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, P P, Rr Rr Rd P, b P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
Operands
Rd, Rr Rd, K Rd, X Rd, X+ Rd, -X Rd, Y Rd, Y+ Rd, -Y Rd, Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q, Rr k, Rr
Description
Move between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit Load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half-carry Flag in SREG Clear Half-carry Flag in SREG No Operation Sleep Watchdog Reset
Operation
Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/Timer)
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None
# Clocks
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATA TRANSFER INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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AT90S2313
Ordering Information
Speed (MHz) 4 Power Supply 2.7 - 6.0V Ordering Code AT90S2313-4PC AT90S2313-4SC AT90S2313-4PI AT90S2313-4SI 10 4.0 - 6.0V AT90S2313-10PC AT90S2313-10SC AT90S2313-10PI AT90S2313-10SI Package 20P3 20S 20P3 20S 20P3 20S 20P3 20S Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 20P3 20S 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
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0839IS-AVR-06/02
Packaging Information
20P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 25.984 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 25.493 Note 2 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note 2 NOTE
2.540 TYP
09/28/01 TITLE 2325 Orchard Parkway 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual San Jose, CA 95131 Inline Package (PDIP) DRAWING NO. REV. 20P3 B
R
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AT90S2313
0839IS-AVR-06/02
AT90S2313
20S
20S, 20-lead, Plastic Gull Wing Small Outline (SOIC), 0.300" body. Dimensions in Millineters and (Inches)* JEDEC STANDARD MS-013
0.51(0.020) 0.33(0.013)
7.60 (0.2992) 10.65 (0.419) 7.40 (0.2914) 10.00 (0.394) PIN 1 ID
PIN 1
1.27 (0.050) BSC
13.00 (0.5118) 12.60 (0.4961)
2.65 (0.1043) 2.35 (0.0926)
0.30(0.0118) 0.10 (0.0040)
0 ~ 8
0.32 (0.0125) 0.23 (0.0091)
1.27 (0.050) 0.40 (0.016) *Controlling dimension: Inches
REV. A
04/11/2001
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0839IS-AVR-06/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
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0839IS-AVR-06/02 0M

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